AAYUSH

PROFESSIONAL SUMMARY

I have done engineering in electronics and instrumentation specialization from Burdwan University, West Bengal in 2019, along with I have hands-on training experience in design and verification in VLSI domain.

PROJECTS

• Project-1: Title : FIFO (First in First Out)

Tool used : Riviera-Pro

Duration : 2 Weeks

Languages : Verilog and System Verilog

Description : A memory in which the data word that is written in first comes out first Is a first-in first-out memory. In digital engineering, there is a constantly recurring problem of synchronisation two System that work at different frequencies. Concurrent read/write FIFO’s can also handle the data exchange between two system of different frequencies.

Project-2:

Title : Verification of AMBA-Advanced Peripheral Bus (APB) Protocol

Tool used : Riviera-Pro

Duration : 1 Week

Language : System Verilog Methodology : UVM

Description : AMBA APB addresses the requirements of low performance synthesizable designs. It is a bus interface that supports a single bus master and multiple slaves and provides lowbandwidth operation. 

• Project-3:

Title : Verification of AMBAAdvanced High-Performance Bus (AHB) Lite

Tool used : Riviera-Pro

Duration : 2 Weeks

Language : System Verilog Methodology : UVM

Description : AMBA AHB-Lite addresses the requirements of high performance synthesizable designs. It is a bus interface that supports a single bus master provides high-bandwidth operation.